ESPCLOCK4 - Design

The idea for ESPCLOCK4 came after encountering this article. It made me realize the successor to the ESP8266 - the ESP32 - has an ultra low power (ULP) coprocessor that can perform simple processing eg. toggle pins, read ADC etc. while the power hungry main CPU is in deep sleep.

After reading through the specs, it seems the ULP can substitute for the ATtiny85 in the ESPCLOCK3 design. The advantage is that the I2C bus is not longer required, and the circuitry can be vastly simplified.

Just like the watchdog timer on the ATtiny85, it appears the real-time clock (RTC) that drives the ULP is not very accurate (5% jitter). However, I think I can use the same calibration technique employed to adjust OCR1A on the ATtiny85 in the ESPCLOCK2 design to dynamically tune the RTC. Basically, by using the difference between the computed network time and actual network time, the RTC counter can be increased or decreased accordingly.

So here's the preliminary design. The ESP32 will again serve only as the conduit to the Internet to retrieve the network time. It will be in deep sleep otherwise to conserve power.

The ULP will perform 3 tasks:

It will advance the physical clock by generating the tick pulses.

It will check to see if battery voltage is low. If so, it will wake ESP32 up, which will write the physical clock time to EEPROM and shutdown.

It will monitor a reset button and perform a software reset when the button is pressed.

As before, a supercapacitor will be used to supply power to the circuit until the ESP32 has time to properly shutdown when power is removed.

I am interested to see what's the power profile of this approach compared to ESP8266 + ATtiny85.

ESPCLOCK1 / ESPCLOCK2 / ESPCLOCK3 / ESPCLOCK4

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