ESPCLOCK2, Part 2 - Interrupt-driven time keeping

Due to the time sensitive nature of I2C, everything we do in the ATtiny85 has to be interrupt-driven. We cannot use any delay() in the code.

The ATtiny85 has two timers, Timer0 and Timer1. We will use Timer0 to drive the clock pins, and Timer1 to keep time.

First we configure Timer1 to interrupt every second:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

#define TIMER1_PRESCALER 4096 #define OCR1A_DEFVAL ((byte)(F_CPU / (float)TIMER1_PRESCALER * 1.0) - 1) // Reset prescalers for Timer1 GTCCR |= bit(PSR1); // Setup Timer1 TCCR1 = 0; TCNT1 = 0; OCR1A = OCR1A_DEFVAL; OCR1C = OCR1A_DEFVAL; TCCR1 = bit(CTC1) | bit(CS13) | bit(CS12) | bit(CS10); // Start Timer1 in CTC mode; prescaler = 4096; // Interrupt on compare match with OCR1A TIMSK |= bit(OCIE1A);

Then in the ISR for Timer1, we simply keep track of the actual time (we call this nettime, or actual time from the network that we are trying to get the clock face to match).

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

volatile byte nettime[3]; // network clock time // Interrupt service routine for Timer1 ISR(TIMER1_COMPA_vect) { incClockTime(nettime[HH], nettime[MM], nettime[SS]); } void incClockTime(volatile byte& hh, volatile byte& mm, volatile byte& ss) { if (++ss >= 60) { ss = 0; if (++mm >= 60) { mm = 0; if (++hh >= 12) { hh = 0; } } } }

We configure Timer0 to interrupt every 200ms:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

#define TIMER0_PRESCALER 1024 #define OCR0A_DEFVAL ((byte)(F_CPU / (float)TIMER0_PRESCALER * 200/1000.0) - 1) // Reset prescalers for Timer0 GTCCR |= bit(PSR0) // Setup Timer0 (but don't run it yet) TCCR0A = 0; TCCR0B = 0; TCNT0 = 0; TCCR0A = bit(WGM01); // CTC mode OCR0A = OCR0A_DEFVAL; // Interrupt on compare match with OCR0A and OCR1A TIMSK |= bit(OCIE0A);

Then when we need to move the second hand by one tick, we do this:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

volatile byte clocktime[3]; // physical clock time volatile byte timer0_tickpin = PB3; incClockTime(clocktime[HH], clocktime[MM], clocktime[SS]); digitalWrite(timer0_tickpin, HIGH); // Set prescaler to 1024, thereby starting Timer0 TCCR0B = bit(CS02) | bit(CS00); ISR(TIMER0_COMPA_vect) { digitalWrite(timer0_tickpin, LOW); timer0_tickpin = (timer0_tickpin == PB3 ? PB4: PB3); // Set prescaler to 0, thereby stopping Timer0 TCCR0B = 0; }

This is essentially doing the same as the following without using delay():

1 2 3 4 5 6 7 8 9

byte tickpin = PB3; digitalWrite(tickpin, HIGH); delay(200); digitalWrite(tickpin, LOW); delay(200); tickpin = (tickpin == PB3 ? PB4: PB3);

The 200ms interval was picked after doing some stress tests witht the clock. 50ms, 100ms and 150ms resulted in some missed ticks when done in quick succession, while 200ms nailed all the tests.

Note that the Timer0 interrupt is enabled/disabled when required. Initially I tried turning off the Timer0 interrupt by setting OCIE0A in TIMSK to 0. This worked, as in the interrupt is indeed disabled, but OCR0A continues to run, resulting in inconsistent timing when interrupt is enabled again. Later, I found out that setting TCCR0B to 0 is the correct way to stop Timer0 when required.

ESPCLOCK1 / ESPCLOCK2 / ESPCLOCK3 / ESPCLOCK4